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| D602 3V, 6GHz Divide-by-2 Static Prescaler Final Applications 5GHz WLAN, IEEE 802.11a and HIPERLAN VSAT at 3.6 to 4.2 GHz Satellite Communications at 4.5 to 4.8 GHz 5 Gbps Clock Generator Product Description The D602 is a SiGe divide-by-2 low noise static prescaler capable of operation up to 6.0 GHz. The D602 operates over a wide range of input frequencies and levels, and provides differential outputs for low noise operation with the common PLL style frequency synthesizer ICs. The static nature of the prescaler prevents spurious generation. The D602 prescaler can operate from either a single positive or single negative supply with power down mode for low standby power consumption. Features Low Phase Noise, -141dBc/Hz at 1kHz offset Single Supply Voltage, 2.7 - 4.0 V Low Power Consumption, 42mW Power Down Mode, 0.2A Compatible with common PLL synthesizer ICs 8-Pin Plastic SOIC Package Ordering Information Type D602 Package 8-Pin SOIC Remark Plastic Package Functional Block Diagram VCC PWD In fIn In /2 Out fOut Out VEE VEE 20-DST-01 Rev 5.0 Sept/01 1 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Pin Out Diagram VCC In In VEE 1 2 3 4 D602 8 7 6 5 PWD Out Out VEE Pin Out Description Pin No. 1 2 3 4 5 6 7 8 Name VCC In In Description Power Supply Voltage Input Prescaler Input (internally-biased) Prescaler Complementary Input (internally-biased) Ground for Input (pins 4 and 5 must be connected to the same potential) Ground for Output (pins 4 and 5 must be connected to the same potential) Complementary Output (open-collector) Output (open-collector) Power Down high impedance CMOS input. When PWD is high, the part is powered down. VEE VEE Out Out PWD Absolute Maximum Ratings Operation in excess of any one of above Absolute Maximum Ratings may result in permanent damage. This device is a high performance RF integrated and is ESD sensitive. The RF inputs on this device are Class 0 ESD rated; therefore suitable precaution should be taken during handling, assembly and testing. Symbol Supply Voltage Voltage on any pin with respect to VEE Differential input voltage Storage Temperature Parameter Min. -0.3 -0.3 -2.0 -65 Max. +4.3 VCC + 0.3 +2.0 +150 Unit V V V C 20-DST-01 Rev 5.0 Sept/01 2 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Electrical Characteristics Conditions: VCC = 3.0V, -40C < TA < 85C unless otherwise specified Symbol VCC TA ICC ICC - PWDN fIn(U) fIn(L) fOsc PIn(U) PIn(L) POut VIH VIL IIH IIL PN Supply Voltage Operating Temperature Supply Current Power-Down Supply Current (VPWD = High) Upper Limit of Input Frequency Lower Limit of Input Frequency Self Oscillation Output Frequency Upper Limit of Input Power Lower Limit of Input Power Output Power High-Level PWD Input Voltage Low-Level PWD Input Voltage High-Level PWD Input Current Low-Level PWD Input Current Residual Phase Noise at 1kHz offset from a 2.5GHz (fOut) carrier -100.0 -100.0 -141 4 -15.0 VCC - 0.2 0.2 100.0 100.0 2 2 3 0 5.8 1 Parameter Note Min. 2.7 -40 Typ. 3.0 25 14 0.2 6.4 0.6 1.0 3 -20 -10 0 1.0 Max. 4.0 85 18 1.0 Unit V C mA A GHz GHz GHz dBm dBm dBm V V nA nA dBc/Hz Notes: (1) Sample Tested (2) For a sine-wave input (3) Since the input signal is AC coupled, in the absence of an RF input, the prescaler may self oscillate and provide an output at this frequency. Self oscillation can be eliminated by powering down the prescaler, or applying a differential DC input voltage (a 47k resistor placed between pin 3 and VCC). (4) This power is delivered to a 50 load. It excludes the power dissipated in the external pull-up resistors. Test Circuit 100p VCC 100p 100n 51 1 Signal Generator 2 8 100n 51 1n 1p D602 7 6 5 1n 1n 3 4 50 Ohm Measurement Equipment 20-DST-01 Rev 5.0 Sept/01 3 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Typical Performance Characteristics Supply Current vs Supply Voltage 17 16 Upper Limit of Input Frequency vs Supply Voltage PIn = - 10dBm 6.9 6.7 Input Frequency [GHz] 6.5 6.3 6.1 5.9 5.7 Supply Current [mA] 15 14 13 12 11 10 9 8 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 5.5 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 Supply Voltage [V] Supply Voltage [V] Input Power Limits vs Input Frequency -2 Output Power vs Supply Voltage fIn = 5.0 GHz -3 10 PIn(U) Output Power [dBm,] Input Power [dBm] 0 -10 -20 -30 -40 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 -4 -5 -6 -7 -8 -9 -10 -11 -12 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 PIn(L) Input Frequency [GHz] Supply Voltage [V] Output Power vs Input Frequency 0 6.7 6.6 Input Frequency [GHz] 6.5 6.4 6.3 6.2 6.1 6 5.9 5.8 1.0 2.0 3.0 4.0 5.0 6.0 7.0 Upper Limit of Input Frequency vs Temperature Output Power [dBm] -5 2.7V 3.0V -10 -15 0.0 Input Frequency [GHz] 5.7 -40 -20 0 20 40 60 80 Temperature [C] 20-DST-01 Rev 5.0 Sept/01 4 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Minimum Required Supply Voltage vs Temperature (fIn = 5.0 GHz) 2.2 -3 -3.5 2.15 Output Power [dBm] Supply Voltage [V] Output Power vs Temperature (fIn = 5.0 GHz) -4 -4.5 -5 -5.5 -6 -6.5 2.1 2.05 2 -40 -20 0 20 40 60 80 Temperature [C] -7 -40 -20 0 20 40 60 80 Temperature [C] Supply Current vs Temperature 14 13.9 13.8 13.7 13.6 13.5 13.4 13.3 Residual Phase Noise Supply Current [mA] -40 -20 0 20 40 60 80 Temperature [C] 20-DST-01 Rev 5.0 Sept/01 5 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Typical Application Information +3V VCO RF 50 50 1 1n * 47k 2 3 4 8 10p 10p 10p D602 7 6 5 10p PLL Frequency Synthesizer Ref. * The 47k resistor provides a DC offset that disables self oscillation in the absence of an RF input. Cascading D602 Prescalers D602 prescalers can be cascaded to achieve division ratios other than 2. For example two D602 prescalers can be used as shown in the following diagram to perform frequency division by 4. +3V PWD 50 50 50 1 In 10p 8 50 1n 10p 1 2 3 10p 4 8 1n 2 3 4 D602 7 6 5 D602 7 6 5 10p Out 10p 10p 20-DST-01 Rev 5.0 Sept/01 6 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final Package Information Package dimensions in millimeters (inches) 8-Lead Plastic SOIC SiGe D602 XXXXXXX Packing Details Note : Refer to JEDEC MS-012 for additional information 20-DST-01 Rev 5.0 Sept/01 7 of 8 D602 3V, 6GHz Divide-by-2 Static Prescaler Final http://www.sige.com Headquarters: Canada Phone: +1 613 820 9244 Fax: +1 613 820 4933 2680 Queensview Drive Ottawa ON K2B 8J9 Canada sales@sige.com San Diego Phone: +1 858 668 3541 Fax: +1 858 668 3546 Hong Kong Phone: +1 852 9177 1917 United Kingdom South Building, Walden Court Parsonage Lane, Bishop's Stortford Hertfordshire CM23 5DB Phone: +44 1279 464 200 Fax: +44 1279 464 201 Product Preview The datasheet contains information from the product concept specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Preliminary Information The datasheet contains information from the design target specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Final The datasheet contains information from the final product specification. SiGe Semiconductor Inc. reserves the right to change information at any time without notification. Production testing may not include testing of all parameters. Information furnished is believed to be accurate and reliable and is provided on an "as is" basis. SiGe Semiconductor Inc. assumes no responsibility or liability for the direct or indirect consequences of use of such information nor for any infringement of patents or other rights of third parties, which may result from its use. No license or indemnity is granted by implication or otherwise under any patent or other intellectual property rights of SiGe Semiconductor Inc. or third parties. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SiGe Semiconductor Inc. products are NOT authorized for use in implantation or life support applications or systems without express written approval from SiGe Semiconductor Inc. RangerCharger , StreamCharger , PointCharger , and LightCharger Copyright 2002 SiGe Semiconductor All Rights Reserved TM TM TM TM are trademarks owned by SiGe Semiconductor Inc. 20-DST-01 Rev 5.0 Sept/01 8 of 8 |
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